A Built-In Redundancy-Analysis Scheme for RAMs with Two-Level Redundancy
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چکیده
With the increasing demand of memories in system-onchip (SOC) designs, developing efficient yield-improvement techniques for memories becomes an important issue. Built-in self-repair (BISR) technique has become a popular method for repairing defective embedded memories. To allocate redundancy efficiently, built-in redundancy-analysis (BIRA) function is usually needed for designing a BISR scheme. This paper presents an efficient BIRA scheme for RAMs with two-level redundancy. Experimental results show that the repair rate of the proposed BIRA scheme approximates to that of the exhaustive search with the same redundancy organization. Furthermore, the repair rate of the proposed BIRA scheme with two-level redundancy is higher than that of the exhaustive search scheme with one-level redundancy. The area cost of the proposed BIRA scheme is low. For example, the hardware overhead of the proposed BIRA scheme for an 8K 64-bit RAM with three spare rows, three spare columns, and two spare words is only about 2%.
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تاریخ انتشار 2006